The present invention relates generally to multistage analog-to-digital converters (ADCs), and more particularly to techniques for improving the linearity of such circuits.
Analog-to-digital converters (ADCs) convert an analog input signal into a corresponding digital output signal. ADCs are often configured as multistage circuits, with each stage determining one or more bits of the digital output signal. The first stage of such a multistage ADC receives a sampled representation of the analog input signal and provides an output representing one or more bits of the digital output signal. The first stage also generates a so-called xe2x80x9cresiduexe2x80x9d which is supplied to the second stage. The second stage utilizes the residue received from the first stage to provide an output representing one or more additional bits of the digital output signal. Similarly, each of the remaining stages other than the final stage generates a residue for use by a subsequent stage. Each stage of a multistage ADC may produce more bits than the output of that stage represents in the digital output signal, thereby providing information redundancy for use in error correction. A digital error correction circuit within the multistage ADC receives the bits generated by each stage, applies the error correction, and generates the digital output signal.
It is well known that pipelining may be applied to a multistage ADC in order to provide an increased throughput. For example, the multiple stages may be configured to utilize parallel processing, at the cost of an initial latency as required to fill the pipeline. A multistage ADC which implements pipelining is referred to herein as a pipelined ADC.
Techniques for reducing non-linearity in a multistage ADC without adversely affecting dynamic range are disclosed in U.S. Pat. No. 6,172,629, issued Jan. 9, 2001 in the name of inventor H. Scott Fetterman and entitled xe2x80x9cMultistage analog-to-digital converter employing dither,xe2x80x9d which is incorporated by reference herein. An illustrative embodiment described in U.S. Pat. No. 6,172,629 utilizes a slicing circuit adapted to slice a signal into a number of different levels based on a selected threshold, and employs dither to vary at least one slicing level in the slicing circuit. As a result, spurious tones are reduced in magnitude and spread out in frequency, and substantially the entire frequency range of the ADC is available for signal bandwidth.
Despite the considerable advantages provided by the techniques disclosed in U.S. Pat. No. 6,172,629, a need remains for further improvements in reducing the non-linearity of a multistage ADC. For example, improved techniques are particularly desirable in applications involving high input levels and significant amounts of component mismatch.
The present invention provides an improved multistage analog-to-digital converter (ADC) and associated method.
In accordance with one aspect of the invention, the ADC includes a sampling circuit and a plurality of stages. A first one of the stages receives a sampled analog input signal from the sampling circuit, and each of the stages operates to generate an output corresponding to one or more bits of a digital output signal representative of the analog input signal. Each of at least a subset of the stages has associated therewith at least one amplifier circuit, e.g., an output analog residue amplifier, having at least one sampling component and at least one feedback component. The sampling component and the feedback component are periodically swapped to reduce gain error between one or more of the stages, thereby providing improved linearity for the ADC.
In an illustrative embodiment of the invention, the sampling component and the feedback component are periodically swapped by randomly selecting at each of a number of points in time a particular one of two available components for utilization as one of the sampling component and the feedback component, with the other of the two available components being the other of the sampling component and the feedback component.
Advantageously, the invention provides reduced non-linearity and hence improved spurious free dynamic range (SFDR) for a multistage ADC. More specifically, the invention in the illustrative embodiment can be used to achieve a non-linearity on the order of 14 bits, which corresponds to approximately 0.03%. The improvements in SFDR are particularly significant for high input levels and in the presence of substantial component mismatch. In addition, the invention can be used to greatly reduce the size of the sampling and feedback capacitors required in a given ADC implementation, which in turn improves conversion speed and reduces silicon area. The invention can be implemented in a wide variety of multistage ADC architectures, regardless of operating frequency.